FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
2.7
CE/MPU Communication
Figure 30 shows the functional relationships between the CE and the MPU. The CE is controlled by the
MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generating a
sum by completing an accumulation interval determined by SUM_CYCLES[5:0] * PRE_SAMPS[1:0] samples.
Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section 5.3 CE Interface Description for additional information on setting up the device using the
MPU firmware.
VAR
(DIO7)
PULSES
W (DIO6)
APULSEW
APULSER
EXT PULSE
SAG CONTROL
MPU
DISPLAY (Memory
mapped LCD
segments)
SERIAL
(UART0/1)
ADC
Mux Control
SAMPLES
CE
DATA
CE BUSY
XFER BUSY
INTERRUPTS
EEPROM
(I 2 C)
DIO
I/O RAM (Configuration RAM)
Figure 30: MPU/CE Communication
Rev 2
67
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